109 lines
3.6 KiB
XML
109 lines
3.6 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="4.0.0" version="1.0">
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This file is intended to be loaded by Logisim-evolution v4.0.0(https://github.com/logisim-evolution/).
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<lib desc="#Wiring" name="0">
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<tool name="Pin">
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<a name="appearance" val="classic"/>
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</tool>
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</lib>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#TTL" name="6"/>
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<lib desc="#TCL" name="7"/>
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<lib desc="#Base" name="8">
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<tool name="Text Tool">
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<a name="valign" val="top"/>
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</tool>
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</lib>
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<lib desc="#BFH-Praktika" name="9"/>
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<lib desc="#Input/Output-Extra" name="10"/>
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<lib desc="#Soc" name="11"/>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="8" map="Button2" name="Poke Tool"/>
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<tool lib="8" map="Button3" name="Menu Tool"/>
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<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="8" name="Poke Tool"/>
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<tool lib="8" name="Edit Tool"/>
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<tool lib="8" name="Wiring Tool"/>
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<tool lib="8" name="Text Tool">
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<a name="valign" val="top"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin"/>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="type" val="output"/>
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</tool>
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<sep/>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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<tool lib="1" name="XOR Gate"/>
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<tool lib="1" name="NAND Gate"/>
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<tool lib="1" name="NOR Gate"/>
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<sep/>
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<tool lib="4" name="D Flip-Flop"/>
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<tool lib="4" name="Register"/>
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</toolbar>
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<circuit name="main">
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<a name="appearance" val="logisim_evolution"/>
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<a name="circuit" val="main"/>
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<a name="circuitnamedboxfixedsize" val="true"/>
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<a name="simulationFrequency" val="1.0"/>
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<comp lib="0" loc="(130,170)" name="Constant"/>
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<comp lib="0" loc="(130,210)" name="Constant">
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<a name="value" val="0x0"/>
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</comp>
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<comp lib="0" loc="(130,270)" name="Constant">
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<a name="value" val="0x0"/>
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</comp>
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<comp lib="0" loc="(370,190)" name="Constant"/>
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<comp lib="1" loc="(210,170)" name="NOT Gate"/>
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<comp lib="1" loc="(210,210)" name="NOT Gate"/>
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<comp lib="1" loc="(310,190)" name="OR Gate"/>
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<comp lib="1" loc="(460,250)" name="AND Gate"/>
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<comp lib="5" loc="(540,250)" name="LED"/>
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<comp lib="8" loc="(100,197)" name="Text">
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<a name="text" val="B"/>
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<a name="valign" val="top"/>
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</comp>
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<comp lib="8" loc="(100,261)" name="Text">
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<a name="text" val="C"/>
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<a name="valign" val="top"/>
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</comp>
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<comp lib="8" loc="(101,161)" name="Text">
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<a name="text" val="A"/>
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<a name="valign" val="top"/>
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</comp>
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<comp lib="8" loc="(301,137)" name="Text">
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<a name="text" val="(A'+B')"/>
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<a name="valign" val="top"/>
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</comp>
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<comp lib="8" loc="(484,197)" name="Text">
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<a name="text" val="(A'+B') . C"/>
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<a name="valign" val="top"/>
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</comp>
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<wire from="(130,170)" to="(180,170)"/>
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<wire from="(130,210)" to="(180,210)"/>
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<wire from="(130,270)" to="(410,270)"/>
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<wire from="(210,170)" to="(260,170)"/>
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<wire from="(210,210)" to="(260,210)"/>
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<wire from="(310,190)" to="(370,190)"/>
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<wire from="(370,190)" to="(370,230)"/>
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<wire from="(370,230)" to="(410,230)"/>
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<wire from="(460,250)" to="(540,250)"/>
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</circuit>
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</project>
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