202410715272-FENAUDRY-LUTHFIYAH-GUSTI-DZAKIRAH/PSD_202410715272
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Upload files to "praktikum-1"

Browse Source
This commit is contained in:
202410715272 FENAUDRY LUTHFIYAH GUSTI DZAKIRAH 2025-12-22 19:56:37 +07:00
parent 3f01af5601
commit 445292a1c8
2 changed files with 92 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
praktikum-1/TUGAS PSD GERBANG LOGIKA - FENAUDRY LUTHFIYAH G.D - 202410715272.pdf Normal file
View File

Binary file not shown.

92
praktikum-1/praktikum1.circ Normal file
View File

@ -0,0 +1,92 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(230,240)" name="Constant">
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(230,280)" name="Constant"/>
<comp lib="0" loc="(230,320)" name="Constant"/>
<comp lib="1" loc="(400,260)" name="OR Gate"/>
<comp lib="1" loc="(450,260)" name="NOT Gate"/>
<comp lib="1" loc="(560,280)" name="AND Gate"/>
<comp lib="5" loc="(590,280)" name="LED"/>
<comp lib="8" loc="(115,125)" name="Text">
<a name="text" val="NPM: 202410715022"/>
</comp>
<comp lib="8" loc="(125,100)" name="Text">
<a name="text" val="Nama: Siti Indri Rahma"/>
</comp>
<comp lib="8" loc="(195,285)" name="Text">
<a name="text" val="B"/>
</comp>
<comp lib="8" loc="(195,325)" name="Text">
<a name="text" val="C"/>
</comp>
<comp lib="8" loc="(196,244)" name="Text">
<a name="text" val="A"/>
</comp>
<wire from="(230,240)" to="(350,240)"/>
<wire from="(230,280)" to="(350,280)"/>
<wire from="(230,320)" to="(480,320)"/>
<wire from="(400,260)" to="(420,260)"/>
<wire from="(450,260)" to="(510,260)"/>
<wire from="(480,300)" to="(480,320)"/>
<wire from="(480,300)" to="(510,300)"/>
<wire from="(560,280)" to="(590,280)"/>
</circuit>
</project>